The role of two-cycle simulation in the S/390 verification process

Microprocessor design techniques have evolved to a point where large systems, such as S/390@ servers, can be constructed using relatively few, but very complex, applicationspecific integrated circuits (ASICs). Delivery of a quality design in a timely fashion requires that several design activities progress simultaneously, with different types of verification used within the various design disciplines. This paper discloses a simulation method capable of functionally verifying a physical implementation of the design at a system level. The aggressive design schedule undertaken on the S/390 Parallel Enterprise Server G4 program required additional advances in simulation beyond those employed in the development of the IBM Enterprise System/9000@ (ES/9000@) processor family. A new type of cycle simulation was developed to supplement the incumbent strategy of using conventional cycle simulation to verify system function combined with Boolean equivalence tools to perform logicalto-physical comparisons. This two-cycle simulation method was invented to verify areas such as logic built-in self-test (LBIST), array built-in self-test (ABET), clock trees, firmware level-sensitive scan design (LSSD) rings, and large custom arrays, which are typically omitted by existing system verification methods. The creation of the two-cycle simulation model is discussed, along with several uses of the model and the types of errors uncovered.